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Dynamic random-access memory
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161	Staged Reads : Mitigating the Impact of DRAM Writes on DRAM Reads ∗ Niladrish Chatterjee University of Utah Naveen Muralimanohar Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2012-01-10 00:00:20 Dynamic random-access memory CPU cache Random-access memory Write buffer Memory controller CAS latency Memory hierarchy DDR3 SDRAM RLDRAM Computer memory Computer hardware Computing
162	Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access ∗ Niladrish Chatterjee‡ ‡ University Manjunath Shevgoor‡ Rajeev Balasubramonian‡ Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2012-11-05 13:54:51 Digital media DDR3 SDRAM DIMM Synchronous dynamic random-access memory Dynamic random-access memory DDR SDRAM CAS latency DDR2 SDRAM Prefetch buffer Computer memory Computer hardware Computing
163	UNIFIED MEMORY ARCHITECTURE Summary The O2™ system Unified Memory Architecture (UMA) represents a radical departure from that of earlier workstations or personal computers. The traditional workstation uses multiple hi Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 2003-03-12 08:39:22 Graphics hardware Silicon Graphics Video card SGI O2 Bus Dynamic random-access memory Computer workstations Shared graphics memory Computer hardware Motherboard Computer memory
164	TORNADO-E6202/E6203 Ultra-high Performance TMS320C6202/C6203 Embedded DSP Controllers Ultimate DSP Development Solutions • Add to Reading List Source URL: www.mlabsys.com Language: English - Date: 2012-04-06 12:43:57 Computing Digital signal processors Embedded systems Electronics manufacturing Joint Test Action Group Texas Instruments TMS320 Synchronous dynamic random-access memory Dynamic random-access memory Static random-access memory Computer memory Computer hardware Electronics
165	MemZip: Exploring Unconventional Benefits from Memory Compression ∗ Ali Shafiee Meysam Taassori Rajeev Balasubramonian University of Utah Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2014-01-10 15:50:12 CPU cache Dynamic random-access memory Memory bandwidth DDR3 SDRAM UltraSPARC III Data structure alignment CAS latency POWER1 Random-access memory Computer memory Computer hardware Computing
166	COMPUTING PRACTICES Itsy: Stretching the Bounds of Mobile Computing A prototype pocket computer that has enough processing power and memory Add to Reading List Source URL: www.tim-mann.org Language: English - Date: 2006-11-21 14:59:12 Itsy Pocket Computer Energy conservation Power management IPAQ Device driver Operating system Dynamic random-access memory Universal Serial Bus Nintendo DS Computer hardware Computing Technology
167	Managing DRAM Latency Divergence in Irregular GPGPU Applications Niladrish Chatterjee∗†§ , Mike O’Connor†k§ , Gabriel H. Loh‡, Nuwan Jayasena‡ and Rajeev Balasubramonian∗ ∗ University of Utah † NVIDI Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2014-08-15 10:13:33 Dynamic random-access memory Scheduling CAS latency Memory controller Latency SDRAM latency GDDR5 CPU cache Random-access memory Computer memory Computer hardware Computing
168	Overcoming the Challenges of Crossbar Resistive Memory Architectures Cong Xu†, Dimin Niu†, Naveen Muralimanohar¶, Rajeev Balasubramonian]¶, Tao Zhang†, Shimeng Yu‡, Yuan Xie§† †Pennsylvania State Universit Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2015-01-18 14:27:24 Digital media Dynamic random-access memory Synchronous dynamic random-access memory Resistive random-access memory Phase-change memory Random-access memory Memristor CPU cache Cell Computer memory Computer hardware Computing
169	TORNADO-E6414/E6415/E6416 Ultra-high Performance TMS320C6414/C6415/C6416 DSP Controllers for Embedded DSP Applications Ultimate DSP Development Solutions features Add to Reading List Source URL: www.mlabsys.com Language: English - Date: 2012-04-06 12:44:03 Computer architecture Embedded systems Integrated circuits Electronics manufacturing Joint Test Action Group Texas Instruments TMS320 PHY Synchronous dynamic random-access memory Booting Electronics Electronic engineering Digital signal processors
170	Quantifying the Relationship between the Power Delivery Network and Architectural Policies in a 3D-Stacked Memory Device Manjunath Shevgoor Jung-Sik Kim Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2013-11-01 14:03:29 Computing Dynamic random-access memory DDR3 SDRAM Memory controller Power network design Three-dimensional integrated circuit DIMM Random-access memory DDR4 SDRAM Computer memory Computer hardware Digital media

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